The RN5200 client and AP chipsets consist of two chipsa highly integrated RF chip and a baseband/MAC ICeach built on the standard 0.18-micron, 1.8-volt CMOS process. RN5200 chipsets include a fully compliant 802.11a OFDM modem delivering speeds of 6, 9, 12, 18, 24, 36, 48 and 54Mbps and support the 5.15-5.35GHz UNII bands. The modem also contains proprietary algorithms optimized for Zero-IF system performance with patent-pending DC offset removal and IQ imbalance correction.
The Resonext RN5200 chipset family forms an end-to-end wireless LAN solution, as it utilizes the same design for WLAN client and Access Point (AP) platforms. The RN5200 is marketed to WLAN network equipment suppliers, Original Equipment Manufacturers (OEMs), Worldwide PC OEMs and Computer Electronics (CE) device manufacturers.
Client Chipset consists of the two-chip combination of the RN5205 RF transceiver and the RN5201 baseband/MAC IC. This chipset supports PC Card, PCI or Mini-PCI interfaces, as well as memory devices including SRAM, ROM, FLASH, SDRAM and EEPROM. Also included are extensive power-management capabilities for ACPI V2.0, host interface, selective clock gating and various low-power modes. The combination of Zero-IF CMOS radio, flexible MAC, AccuChannel equalization, and the complete 802.11i security mechanism, makes this chipset ideal for small form-factor client cards integrated in notebook and small portable platforms.
Chipset consists of the RN5205 RF transceiver and the RN5202 baseband/MAC IC. In addition to a flexible MAC, AccuChannel equalization, and a complete 802.11i security mechanism, the RN5200AP
supports 64MB of external addressable memory for MAC and AP software and supports popular memory types including SRAM, ROM, FLASH, SDRAM and EEPROM. The I/O interface is expanded to include an MII interface to connect an external Ethernet PHY and an RS232 port for configuration. APoC architecture reduces the number of external components by incorporating a dedicated on-chip high-performance ARM922T
processor core for AP functions and software, an Ethernet 802.3 MAC, an MII interface and the entire 802.11a digital subsystem on a single chip. Proprietary on-chip high-speed data path architecture minimizes the latencies typically associated with a conventional AP design using off-the-shelf components. This highly integrated approach significantly reduces the BOM cost for an AP design while producing a high-performance, scalable and flexible system.
-- Stephan Pietzko - Okt. 2002